CD2231 Intel Corporation, CD2231 Datasheet - Page 52

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
5.4.8
5.4.8.1
5.4.8.2
52
Transmit DMA Transfer
The CD2231 contains two DMA descriptors that can be loaded by the CPU to specify transmit
buffers. These descriptors are designated A and B, and each consists of a 32-bit address
(ATBADR/BTBADR), a 16-bit count (ATBCNT/BTBCNT), and an 8-bit status (ATBSTS/
BTBSTS).
The Status register contains an Ownership Status bit — 2231own. When this bit is set the CD2231
owns the descriptor, and it should not be written to by the CPU. When this bit is clear, the
descriptor is owned by the CPU.
When DMA is selected and the channel is enabled, the CD2231 waits for ownership of Buffer A.
When ownership of A is given by setting the 2231own bit, the buffer is transmitted, and the
Ownership bit is cleared. The CD2231 waits for ownership of Buffer B; this process continues,
toggling between the two buffer descriptors.
The DMABSTS register contains a status bit (NtBuf) that informs the CPU of the next buffer to
transmit and to ensure that the CPU and CD2231 stay in synchronization. This procedure ensures
that a pipeline of data is available for the CD2231 to send, maximizing the bandwidth utilization
and minimizing the possibility of underruns.
Interrupts for Transmit DMA Buffers
Two types of transmit interrupts are available in DMA mode; they are enabled by the IER and
controlled by the TxD and TxMpty bits.
When the TxMpty interrupt is enabled, interrupts are generated when there is no transmit data
available to send. For example, the TxMpty interrupt can be used by the CPU to determine when
line turn-around can occur on half-duplex lines.
Normally, the TxDat interrupt is used to indicate the end of each transmit buffer. The interrupt is
scheduled internally when the last data is read from the transmit buffer into the FIFO.
Because only one interrupt is generated for each buffer, the TxD bit (IER[0]) register can be left
permanently enabled. If interrupts are required selectively for individual buffers, the INTR bit in
the ATBSTS/BTBSTS registers can be used to selectively enable interrupts.
Chained Buffers
In Synchronous modes, when the frame size exceeds the maximum buffer size, a frame can be
transmitted from a number of separate buffers. This is achieved simply by not setting the EOF bit
in the ATBSTS/BTBSTS (Transmit Buffer Status register) until the last buffer of the frame. The
CD2231 transmits the buffers as one frame; it appends the CRC only when all the data is
transmitted from the buffer with the EOF flag set.
14. In this example, the third link does not fill the buffer. Thus, when the end-of-frame delimiter is
15. Next, the CD2231 sets the EOB and EOF bits to show that the buffer is complete, and that this
16. The CD2231 optionally interrupts the host with EOF and EOB set in the RISR to indicate that
detected by the CD2231, the value of 40 (for 40 received bytes) is written into the received
byte count — BRBCNT.
is the last link in the chain.
the received frame is complete, and this was the last link in the chain.
Figure 9
illustrates this procedure.
Datasheet