CD2231 Intel Corporation, CD2231 Datasheet - Page 37

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

5.2.1
5.2.2
Datasheet
Contexts and Channels
The registers in the CD2231 are grouped into Global, Virtual, and two sets of Per-Channel
registers. The CD2231 is normally in the background context, where the CAR (Channel Access
register) selects the channel number for the Per-Channel registers. The interrupt context begins
with the interrupt acknowledge bus cycle, and ends with a write access to the appropriate End of
Interrupt register. In the interrupt context, only the Per-Channel registers for the channel number
being serviced are available; the CAR has no effect. Most Global registers are available at all times,
but some are shared by the two channels, such as the FIFO registers. These are called Virtual
registers, and must be accessed only during an interrupt context.
Interrupt contexts can be nested so that a higher-priority interrupt service can preempt a lower-
priority interrupt already in progress. The CD2231 pushes the current interrupt context onto the
stack, visible in the STK (Stack register), and enters the context for the newly acknowledged
interrupt. Any register accesses are in the new interrupt context until the host performs a write to
the appropriate EOIR for the top-level context. The CD2231 then pops the top-level context off the
stack and returns to the previous interrupt context.
Interrupt Registers
The IER (Interrupt Enable register) and the LIVR (Local Interrupt Vector register) are Per-Channel
registers. IER contains bits to enable or disable the various interrupt sources within the CD2231.
The LIVR value is output on the data bus during the interrupt acknowledge cycle. There are sets of
three Global registers that correspond to the three types of interrupts: Receive, Transmit, and
Modem. The Priority Interrupt Level registers — RPILR, TPILR, and MPILR are programmed to
contain the value that is present on the address bus during the interrupt acknowledge bus cycle for
each type of interrupt. The Interrupt Status registers — RISR, TISR, or MISR are examined during
the interrupt service routine to determine the cause of each type of interrupt. The TDR (Transmit
Data) and RDR (Receive Data) registers provide access to the FIFO buffers for each channel.
These registers must not be accessed outside of the proper interrupt context. A write operation to
the End of Interrupt registers — REOIR, TEOIR, or MEOIR must be the last access to the CD2231
at the end of this handler routine to return it to its background context.
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
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