CD2231 Intel Corporation, CD2231 Datasheet - Page 38
CD2231
Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
1.CD2231.pdf
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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
5.2.3
38
Figure 4. Interrupt Acknowledge Cycle
A/D[0–15]
R/W*, CS*
1
DATDIR*
DTACK*
IACKIN*
Interrupt vector is always on A/D[0–7].
IREQn*
A[0–7]
DEN*
DS*
Groups and Types
There are two general reasons for the CD2231 to request service from the host processor — data
transfer and exceptional conditions. Furthermore, interrupts are grouped into three categories, each
with an associated Interrupt Request signal — IREQ1*, IREQ2*, and IREQ3*.
Group 1 is only used for exceptions. Groups 2 and 3 include both data transfer and exceptions.
Table 2
an interrupt request is encoded into the two least-significant bits of the vector presented on the data
bus during the interrupt acknowledge cycle. The most-significant six bits of the vector come from
the LIVR:
Interrupt Vector LSBs
00
01
10
11
•
•
•
Group 1 — Modem signal change/timer events
Group 2 — Transmit interrupts
Group 3 — Receive interrupts
shows the possible causes of transmit and receive interrupt service requests. The cause of
Receive exception
Modem signal change or timer event
Transmit data or exception
Receive Good Data
CD2231
SAMPLES ADDRESS BUS
VECTOR
1
1-CLOCK DELAY
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