CD2231 Intel Corporation, CD2231 Datasheet - Page 131

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
8.5.2.5
8.5.2.6
8.5.2.7
Datasheet
Register Name: RFOC
Register Description: Receive FIFO Output Count
Default Value: x’00
Access: Byte Read only
Register Name: RDR
Register Description: Receive Data
Default Value: x’00
Access: Byte Read only
Register Name: REOIR
Register Description: Receive End of Interrupt
Default Value: x’00
Access: Byte Write Only
TermBuff
Bit 7
Bit 7
Bit 7
D7
0
Receive FIFO Output Count (RFOC)
Bits 7:5
Bits 4:0
Receive Data Register (RDR)
This Virtual register accesses the receive data FIFO of a channel interrupting for receive data
transfer. This register address is used for all channels to transfer receive FIFO data to the host, if
programmed in Interrupt Transfer mode. Data must be read as bytes, and follows the rules listed in
Section 8.3
on A/D[7:0], if BYTESWAP is low, data is valid on A/D[15:8]. This is true because the RDR is on
an even address.
Receive End of Interrupt Register (REOIR)
REOIR — Asynchronous and HDLC Modes
The CD2231 interprets values written to this register at the completion of all receive interrupts.
Bit 7
DiscExc
Bit 6
Bit 6
Bit 6
D6
0
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
for the positioning of valid data on the bus. If the BYTESWAP pin is high, data is valid
Reserved – always returns ‘0’ when read.
Receive data count
If the receive channel is interrupt driven, a non-zero value in this bit field is the num-
ber of data characters available for transfer within the current receive interrupt.
Terminate current DMA buffer
If this bit is set, the current receive buffer is terminated and data transfer is switched
SetTm2
Bit 5
Bit 5
Bit 5
D5
0
SetTm1
RxCt4
Bit 4
Bit 4
Bit 4
D4
NoTrans
RxCt3
Bit 3
Bit 3
Bit 3
D3
RxCt2
Gap2
Bit 2
Bit 2
Bit 2
D2
Motorola Hex Address: x’F8
Motorola Hex Address: x’30
Motorola Hex Address: x’84
RxCt1
Gap1
Bit 1
Bit 1
Bit 1
D1
Intel Hex Address: x’F8
Intel Hex Address: x’33
Intel Hex Address: x’87
RxCt0
Gap0
Bit 0
Bit 0
Bit 0
D0
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