CD2231 Intel Corporation, CD2231 Datasheet - Page 94



Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Intel Corporation
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Register Name: COR3
Register Description: Channel Option Register 3
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 3
Bit 2
Bit 1
Bit 0
Channel Option Register 3 (COR3) — Async-HDLC/PPP Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bits 3:0
Bit 6
RLM – Remote Loop Back mode
RLM = 1 enables Remote Loopback mode
RLM = 0 disables Remote Loopback mode
RtsAO – RTS automatic output enable
If RtsAO = 1, then the RTS* output pin remains enabled during DMA or character
bursts from the transmit FIFO. If the CTS* input pin goes high, then RTS* goes high
and transmission is stopped after the current burst is completed.
CtsAE – CTS automatic enable
When clear, the transmitter output enable is independent of the CTS* input pin.
When set, the CTS* input pin is evaluated prior to the transmission of each character.
If CTS* is asserted low, that character is transmitted completely. If CTS* is high,
that character transmission is held until CTS* goes low.
DsrAE – DSR automatic enable
When clear, the receiver input enable is independent of the DSR* input pin.
When set, the DSR* input pin is evaluated at the end of each received character. If
DSR* is asserted low, the receiver input is enabled for the next character. If DSR*
is high, the receiver is disabled until DSR* goes low.
0 = 1 Stop bit
1 = 2 Stop bit
FCS append
0 = Receive CRC is not passed to the host at the end of the frame
1 = Receive CRC is passed to the host at the end of the frame
RxChk – Receive FCS check enabled
When clear, the channel does not test the 2-byte FCS field. All frame data characters
are given to the host.
When set, the channel tests the 2-byte FCS field.
TxGen – Transmit FCS enabled
When clear, the channel does not add the 2-byte FCS field.
When set, the channel adds the 2-byte FCS field at the end of the frame.
npad3, npad2, npad1, npad0 – Transmit frame leading pads
The number of character times preceding any frame transmission. A character time
is 10 bit times. All zeros in this field disables the leading pads
Bit 5
Bit 4
Bit 3
Bit 2
Motorola Hex Address: x’16
Bit 1
Intel Hex Address: x’15
Bit 0

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