CD2231 Intel Corporation, CD2231 Datasheet - Page 19
Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Table 1. Pin Descriptions (Sheet 3 of 3)
2, 20, 62, 70,
8, 45, 79, 96
37, 41, 42,
47, 64, 65,
18, 22, 36,
61, 63, 66,
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
TRANSMIT CLOCK OUT/DATA TERMINAL READY* [0–1]: This output can
be controlled automatically by the CD2231 to indicate a programmable
threshold has been reached in the receive FIFO. It can also be programmed to
output the transmit data clock. Following reset, this pin is high and stays high in
Clock mode until the transmit channel is enabled for the first time; after which it
remains active, independent of the state of the transmit enable. In all modes,
the clock transitions every bit time, even during idle fill in Asynchronous mode.
Data transitions are made on the negative-going edge of TXCOUT.
RECEIVE CLOCK OUT [0–1]: This output provides a one-time bit rate clock for
the receive data in all modes, except when an input (RXCIN) one-time receive
clock is used. After reset, this pin is low until the channel is receive enabled for
the first time, after which it remains active, independent of the state of receive
enable. When in Asynchronous mode, the output only transitions while receiving
data and not during inter-character fill. The receive data is sampled on the
positive-going edge of this clock.
CLEAR TO SEND* [0–1]: This input can be programmed to control the flow of
transmit data, for out-of-band flow control applications.
CARRIER DETECT* [0–1]: This pin is always visible in the MSVR register. On
the CD2231, these functions are separated onto two pins. When used as CD*,
this input can be programmed to validate receive data.
TRANSMIT CLOCK [0–1]: This pin inputs the transmit clock to the bit rate
RECEIVE CLOCK [0–1]: This pin inputs the receive clock to the bit rate
DATA SET READY* [0–1]: On the CD2231, these functions are separated onto
two pins. When used as DSR*, this input can be programmed to validate
TRANSMIT DATA [0–1]: Serial data output for each channel.
RECEIVE DATA [0–1]: Serial data input for each channel.
BYTESWAP: This pin alters the byte ordering of data during certain 16-bit
transfers and changes the half of the data bus on which byte transfers are made
to comply with Intel
alter the bus handshake signals. When the BYTESWAP pin is high, the byte of
A/D[0–7] precedes that of A/D[8–15] in a string of transmit or receive bytes;
when BYTESWAP is low, A/D[8–15] precedes A/D[0–7].
When the BYTESWAP pin is high, bytes are transferred on A/D[0–7] when A
is low, and on A/D[8–15] when A is high. When BYTESWAP is low, bytes are
transferred on A/D[8–15] when A is low, and A/D[0–7] when A is high. A
different register map is used, depending on the state of this pin.
Byteswap Byte Alignment
NO CONNECTION: Make no connections to these pins. They must be left open
for proper device operation.
EXTERNAL PULL-UP [1–12]: These pins must be terminated to V
resistors for proper device operation. A value of 4.7 k
processor systems. BYTESWAP does not