CD2231 Intel Corporation, CD2231 Datasheet - Page 40



Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Intel Corporation
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Highest priority:
Lowest priority:
Systems with Interrupt Controllers
Some systems use an interrupt controller that supplies its own vector during the interrupt
acknowledge cycle. To function properly, the CD2231 needs an IACK cycle in response to its
interrupt request. These systems can decode three distinct locations from the CD2231 to produce
an IACKIN* instead of CS*. The PILRs should be programmed with the addresses of these three
Alternatively, a single location can be decoded and the three PILRs given identical values as
described earlier. In either case, the host should read one of these locations before the first access to
the device in an interrupt service routine. The CD2231 enters its interrupt acknowledge context for
the proper type and channel, and the data returned is the device interrupt vector from the LIVR.
Multi CD2231 Systems
Multiple CD2231s can be chained together for systems requiring more than two channels. Each
group of interrupt request lines — IREQn* — can be connected in a parallel wired-OR fashion.
The system Interrupt Acknowledge signal is connected to the IACKIN* pin of the first device, its
IACKOUT* is then connected to the IACKIN* of the next device, and so on, forming a chain of
Keep-and-Pass Logic
The acceptance of an interrupt acknowledge cycle by the CD2231 depends on whether the part is
requesting service and whether the least-significant seven address bits match the contents of the
appropriate PILR. The following rules apply to the keep-and-pass logic:
Fair Share Scheme
When multiple CD2231s are chained, the Fair Share logic in these devices guarantees that the
interrupts from all CD2231s in the system are presented to the host with equal urgency. There is no
positional hierarchy in the interrupt scheme. For example, the CD2231 farthest from the host has
an equal chance of getting its interrupts through as the CD2231 nearest to the top of the interrupt
chain. The Fair Share scheme is transparent to the user, and no enabling or disabling is required.
1. If the CD2231 does not have an interrupt asserted, the interrupt acknowledge is passed out on
2. If the CD2231 is asserting one or more of its interrupts, but the interrupt priority levels driven
3. If the CD2231 is asserting an interrupt and the interrupt priority level on the address bus
on the address bus by the host do not match the contents of the appropriate PILR, this interrupt
acknowledge is also passed out on the IACKOUT*.
matches the PILR for that interrupt type, the interrupt acknowledge is accepted by the
CD2231, and the vector from the LIVR is driven onto the data bus.
Receive Interrupt register
Transmit Interrupt register
Modem Interrupt register

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