L64724 LSI Logic Corporation, L64724 Datasheet - Page 100

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.42 External Output Control Bits and Reset Register
3-70
(Group 4: APR 55)
FP_LOCK_LEN
PWRP
Reserved
CLK_ALPHA_SEL
This register contains the control bits for the XCTR_OUT[3:0] external
output pins and the bits that reset the demodulator and FEC circuitry.
Read/Write: R/W
L64724 Registers
APR
55
ADC_BP
D7
Frequency/Phase Lock Detector Length
The FP_LOCK_LEN bit operates in conjunction with the
Carrier Threshold field (Group 4, APR 29) to set the
phase lock detector estimation period. For details, see
Section 5.7.1.5, “Phase Lock Detection,” page
PWRP Signal Invert
The PWRP bit, when set to 1, inverts the polarity of the
signal output on the PWRP pin.
Reserved
You must set the Reserved bits to 0 for normal operation.
Clock Loop Coefficient 0
The CLK_ALPHA_SEL bit configures the coefficient
value (ALPHA) for the Interpolator structure within the
clock recovery loop. When the bit is 0, the value for
ALPHA is 0.43. When the bit is 1, the value for ALPHA
is 0.5. The default value for CLK_ALPHA_SEL is 0.
OB_2C
D6
FP_LOCK_LEN
PWRP
0
1
0
1
D5
PWRP Output Pin
Normal
Inverted
XCTR[3:0]
Estimation Period
Normal (long)
Short
D2
DEMOD_
RST
D1
5-15.
FEC_
RST
D0
[2:1]
4
3