L64724 LSI Logic Corporation, L64724 Datasheet - Page 255

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Equation B.62
Set Group 4, APR 46 to 0x09 and APR 45 to 0x40.
Group 4, APR 47–48 – Set to 0xFBC0.
The value for the lower clock sweep limit, CLK_LSWL[15:0], is set as
explained in the following paragraphs. It should be noted that the lower
sweep limit is an approximate value, but the approximation to the real
sweep limit is accurate enough. Assume that the lower sweep limit
needed is
in
Equation B.63
Set Group 4, APR 48 to 0xFB and APR 47 to 0xC0.
Group 4, APR 49 52 – Set to 0x1E000000.
Choose CLK_BIAS[30:0] according to
Equation B.64
Fs = sampling frequency at the A/D and Fb is the baud rate.
Set Group 4, APR 52 to 0x1E, APR 51 to 0x00, APR 50 to 00, and
APR 49 to 00.
QPSK Demodulator and FEC Configuration Example: Low Data Rates
Equation
CLK_BIAS
CLK_USWL
CLK_BIAS
CLK_LSWL
CLK_USWL
B.63.
10 kHz. The CLK_LSWL[15:0] value is calculated as shown
=
=
=
=
=
F s
---------------------------------------------------------- -
60 10
----------------------------------------------------------
---------------------------------------------------------- 2
60 10
---------------------------------------------------------- -
F s
---------------------------------------------------------- 2
60 10
2
2
2 2.0 10
45
---------------------------- -
DF_RATIO
2
45
---------------------------- -
DF_RATIO
45
6
2 Fb
6
6
sweeplimit
–
1
0.125 2
10 10
10
1
0.125 2
0.125 2
10
6
3
3
2
28
28
2
22
22
22
=
503316480
Equation
2
=
=
–
2368
2368
10
B.64.
10
(0x1E00.0000)
(0x0940)
(0xFBC0)
B-41