L64724 LSI Logic Corporation, L64724 Datasheet - Page 76

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.12 Viterbi Maximum Bit Error Count, Rate 7/8 (Group 4: APR 13)
3-46
proceeds to adjust the phase of the incoming symbol stream until
synchronization is reached. The symbol error count is given by
Equation
Equation 3.7
For example, a value of VMBEC_6_7[7:0] = 00x03 specifies 416 errors.
For more information, see
Note that a software reset (FEC_RST, APR 55, bit 0 set to 1) does not
affect the contents of the register.
Read/Write: R/W
This register specifies the maximum number of Viterbi symbol errors that
are allowed to occur within the data period set by VMDC1 (Group 4, APR
4) to achieve Viterbi module synchronization.
Whenever the symbol error count from the internal bit error counter
exceeds the value VMBEC_7_8[7:0], the synchronization module
concludes that the Viterbi decoder module is out of synchronization and
proceeds to adjust the phase of the incoming symbol stream until
synchronization is reached. The symbol error count is given by
Equation
Equation 3.8
L64724 Registers
APR
12
Number of Symbol Errors
Number of Symbol Errors
Note:
D7
3.7.
3.8.
This register is used during Viterbi code rate acquisition for
Rate 7/8.
Viterbi Maximum Bit Error Count VMBEC_6_7[7:0], Rate 6/7
Section 7.1.3, “Viterbi BER Monitor,” page 7-7.
=
=
128 VMBEC_6_7
128 VMBEC_7_8
+
+
32
32
D0