L64724 LSI Logic Corporation, L64724 Datasheet - Page 142

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

5.6.1.1 Timing Loop Sweep Limits
5-10
Equation 5.5
Equation 5.6
Equation 5.7
During timing acquisition, the internal sweep mechanism can be used.
To vary the sweep rate, change the value in the CLK_SWR register
(Group 4, APR 43 and 44). To start the sweep generator, set the
CLK_SW bit (Group 4, APR 53) to 1.
Equation 5.8
Equation 5.8
The parameter timing_bw refers to the natural frequency
symbol rate (Rb = 1/Tb). Substitute the value of
the above equations for
The CLK_USWL (Group 4, APR 45 and 46) and CAR_LSWL[15:0]
(Group 4, APR 47 and 48) registers set the upper and lower timing loop
sweep limits, respectively.
operation.
Demodulator Module Functional Description
timing _bw
CLK_MU_SEL
CLK_LAMBDA_SEL
b
=
------------------------- -
K
2
dtim
n
L
gives the suggested value for the timing loop bandwidth.
T b
tim
n
CLK_MU_SEL
CLK_LAMBDA_SEL
=
=
l og
2
2
=
l og
Rb MSps
-----------------------------
a
a
2
Figure 5.4
28
and
2
10
b
2
16
b
.
Krad/s
shows the timing loop sweep
n
from
Equation 5.8
n
. Rs is the
into