L64724 LSI Logic Corporation, L64724 Datasheet - Page 25

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

2.4 Control Signals Interface
PLLVDD
PLLVSS
The Control Signals Interface controls the operation of the L64724 and
is not associated with any particular interface.
IDDTN
RESET
XCTR_IN
XCTR_OUT[3] Control Output/Sync Status Flag
Control Signals Interface
PLL Power
PLLVDD is the power supply pin for the PLL module and
is normally connected to the system power (V
PLL Ground
PLLVSS is the ground pin for the PLL module and is
normally connected to the system ground plane.
Test
The IDDTN pin is an LSI Logic internal test pin. Set the
IDDTN pin LOW for normal operation.
Reset
RESET is an active-HIGH signal that, when asserted,
resets all internal data paths. The RESET signal resets
all of the Group 2 and Group 3 registers and some of the
Group 5 register bits. Group 4 registers are unaffected.
RESET timing is asynchronous to the device clocks. The
RESET signal performs the same operation as the reset
bits specified in the Group 4 APR 55 register. PCLK must
be running for RESET to take effect.
Control Input
The XCTR_IN pin is an external input control pin. It is
sensed by reading the XCTR_IN bit (D6) in the Group 3,
APR 6 register.
The XCTR_OUT[3] pin indicates the synchronization
status for one of three synchronization modules in the
L64724. The modules are the Viterbi Decoder, Reed-
Solomon Deinterleaver (DI/RS), and Descrambler. For
any of the three synchronization outputs, the
XCTR_OUT[3] signal, when asserted, indicates that
synchronization has been achieved for the sync module
chosen using the SSS[1:0] bits (Group 4, APR16). When
deasserted, the signal indicates an out-of-synchronization
condition.
DD
) plane.
Output
Input
Input
Input
Input
Input
2-5