L64724 LSI Logic Corporation, L64724 Datasheet - Page 157

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

6.1 Synchronization Scheme
Chapter 6
Decoding Pipeline
Synchronization
This chapter describes the configurable synchronization circuit that aligns
the decoding pipeline outputs to the overall frame structure of the
L64724. The decoding pipeline consists of the Viterbi Decoder,
Deinterleaver, Reed-Solomon (RS) Decoder, and the Descrambler. This
chapter contains the following sections:
The L64724 FEC synchronization scheme is accomplished in three
stages:
A global control module generates the control signals for the Viterbi,
Descrambler, Deinterleaver, and RS Decoder modules. The global
control module handles the appropriate sequencing of the
synchronization signals for determining in- and out-of-synchronization.
The input to the FEC portion of the L64724 is two symbols generated by
the demodulator portion. The maximum information rate is 90 Mbits/s.
Figure 6.1
L64724 Satellite Receiver
Section 6.1, “Synchronization Scheme”
Section 6.2, “Viterbi Decoder Synchronization”
Section 6.3, “Reed-Solomon Deinterleaver Synchronization”
Section 6.4, “Descrambler Synchronization”
The first synchronization stage uses output statistics from the Viterbi
Decoder module.
The second stage identifies a synchronization word.
The third stage identifies an inverted synchronization word.
shows the organization of the synchronization module.
6-1