L64724 LSI Logic Corporation, L64724 Datasheet - Page 264

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

C.2 Serializer Interface Signals and Configuration Registers
C-2
The method used to control the Serializer frees up the external
microprocessor or the on-board microcontroller to perform other critical
operations. Similarly, the Serializer may be used to implement the 3-wire
interface in any of the three modes of the 3-wire interface (see
C.4, “Programming for 3-Wire Mode,” page
The pinouts and a detailed description of the operation of the serializer
are outlined in the following sections.
TXSD[6:0]
TXED[7:0]
STXD[7:0]
XCTR[2] (ENABLE)
Programming the Serializer
Write to APR 61(TXED)—generates the last byte that is to be written,
followed by a STOP condition
TXSD[6:0] provide the 7-bit slave address of the tuner
chip and comes from Group 4, APR 59, of the
microprocessor interface (uPI.) Bit 7 is the MSB of the
slave address. The Serializer module serializes the slave
address and outputs it on XCTR_OUT[1].
The content of this register is the last data of the serial
interface write cycle. It is an 8-bit value stored in
Group 4, APR 61 of the uPI.
This register holds the data that is serialized and sent out
on the serial interface by the Serializer. This value comes
from Group 4, APR 60 of the uPI, and is used when the
uPI or the uC wants to write two or more data bytes to
the tuner.
XCTR[2] is a bit in the Group 4, APR 55 register that
controls the ENABLE signal on the XCTR_OUT[2] pin
within the 3-wire interface. When the ENABLE signal is
HIGH, the data on the data bus is valid.
C-6.)
Section