L64724 LSI Logic Corporation, L64724 Datasheet - Page 221

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

B.2.5 Decimation Control
Table B.2
1. Megasamples per second (MS/s)
2. For Rs <= 44.5 MSps, calculate the sampling rate as follows: from the set of valid sampling frequency
Threshold
7.5 to 3.75
45 to 44.5
44.5 to 30
15 to 7.5
3.75 to 1
30 to 15
(MS/s)
values, (30, 35, 40 ..., 85, 90), select the lower, closest value to 4 * DF_RATIO * Rs/(1 + alpha),
where alpha is the “corner” margin (1%).
Rs
1
DF_RATIO DF_SELECT DF_GAIN
Decimation Procedure
1
1
1
2
4
8
The decimation and the sampling rate are configured to provide the
highest possible number of samples per symbol with the tightest
decimation filter available. The procedure is outlined in
results are shown in
Table B.3
Demodulator Configuration Tips
(Sheet 1 of 3)
(MS/s)
44.5
Rs
45
44
43
42
41
1
0
0
1
2
3
4
Frequency
Sampling
Decimation Results
(MHz)
91.5
90
90
90
90
90
1
1
1
2
4
8
Table
DF_RATIO
10000100 0x84
10000100 0x84
00000100 0x04
00101000 0x28
01010001 0x51
01111010 0x7A
B.3.
Binary
Register 19
Group 4,
1
1
1
1
1
1
Setting
Hex
Samples
Symbol
2.033
2.022
2.045
2.093
2.143
2.195
per
91.5 (N = 1, S = 61,
DF_FILTER
T = 10, M = 3
See footnote
See footnote
See footnote
See footnote
See footnote
0
0
0
0
0
0
Fs (MHz)
Table B.2
DF_GAIN
2
and the
1
1
1
1
1
1
B-7