L64724 LSI Logic Corporation, L64724 Datasheet - Page 54

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table 3.4
3.5.1 Reed-Solomon Corrected Error Count (Group 3: APR 0 and 1)
3-24
APR
(Sheet 2 of 2)
14
15
16
17
18
19
20
21
22
23
D7
Group 3 Register Map (Cont.)
When read, the Reed-Solomon Corrected Error Count (CEC) register
presents the corrected byte or bit error count since it was last reset. The
bit or byte error count is a function of the RS_Bit/Byte_Select
configuration bit (Group 4, APR 31, D7). When the bit error count mode
is chosen, the value in the register represents the bit error count, which
is the CEC multiplied by eight. When written, the register is reset to 0.
The CEC field is 16 bits long. The LSB is located at APR 0, bit 0, and
the MSB at APR 1, bit 7. The CEC count saturates (stops) when it
reaches its maximum count (65,535), and the counter is not reset after
it is read. When the register is written, the CEC bits are cleared to 0.
Read/Write: R/W
L64724 Registers
APR
APR
0
1
D6
Reserved
Reserved
D15
D7
Demodulator SNR Estimate, SNR[7:0]
D5
Reed-Solomon Corrected Error Count high byte, CEC[15:8]
Reed-Solomon Corrected Error Count low byte, CEC[7:0]
uC_Status_byte0 [7:0]
uC_Status_byte1 [7:0]
uC_Status_byte2 [7:0]
uC_Status_byte3 [7:0]
uC_Status_byte4 [7:0]
Reserved
Reserved
D4
Demodulator SNR Estimate, SNR[11:8]
Active
IMQ_
D3
D2
Viterbi Code Rate[2:0]
Reset Value: 0x0000
D1
D0
D0
D8