L64724 LSI Logic Corporation, L64724 Datasheet - Page 37

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.2 Reset and How it Affects Registers
There are three separate resets available on the L64724, as follows:
Each reset affects the registers differently, as follows:
Registers in Group 4 are unaffected by any of the reset operations. The
contents of the Group 4 registers are random immediately after
power-up, and retain their last known value after any of the three reset
operations listed above.
The following steps should be followed when resetting the L64724:
1. Issue an active-HIGH reset pulse to the RESET pin. The reset pulse
2. Program the Configuration (Group 4) registers to their proper values.
3. Issue a soft reset by setting the DEMOD_RST bit and the FEC_RST
4. After the RESET pin has been deasserted (LOW), wait the wake-up
Reset and How it Affects Registers
The hardware RESET pin
The DEMOD_RST register bit (Group 4, APR 55, bit 1)
The FEC_RST register bit (Group 4, APR 55, bit 0).
Toggling the hardware RESET pin resets all of the Group 2 and
Group 3 registers and some of the Group 4 registers. Registers in
Group 4 are unaffected.
Setting the DEMOD_RST bit in the External Output Control bits and
Reset Register (Group 4, APR 55, bit 1) affects only the bits in
Group 3 registers that are directly concerned with the demodulator
circuitry.
Setting the FEC_RST bit in the External Output Control bits and
Reset Register (Group 4, APR 55, bit 0) resets the System
Mode/Status registers (Group 2) and any bits in Group 3 registers
that are directly concerned with the FEC circuitry.
width must be in accordance with the parameter t
Figure
bits to a 1 (Group 4, APR 55). The bits are self-resetting, and do not
have to be cleared.
time amount specified by the parameter t
8.4).
WK
(see
RWH
Figure
(see
8.4).
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