L64724 LSI Logic Corporation, L64724 Datasheet - Page 48

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3-18
APR
0
VBER
D7
S3_LS
Four consecutive read operations must be done to the same Group 2
address (A[2:0] = 0b010) to access all four bytes of the status registers.
The STS register bits are cleared to 0 after a hardware reset. They are
also cleared each time a register byte is read—when you read the eight
LSBs, the eight LSB interrupts are cleared, and when you read the eight
MSBs, the eight MSB interrupts are cleared.
The following register diagram shows the bit organization of STS[7:0].
Descriptions of the bits follow the register diagram.
VBER
S3_LS
S3_S
L64724 Registers
D6
S3_S
D5
Viterbi Bit Error Rate Flag
The L64724 sets the VBER bit when the period specified
by VMDC2 (Group 4—APR 5, 6, and 7) is reached. The
L64724 also generates an interrupt if the VBER_IE bit in
the SMR is set. The L64724 clears the VBER bit to 0
after a reset or a Group 2 (STS) read.
Stage 3 Loss of Synchronization Flag
The L64724 sets the S3_LS bit when the Descrambler
synchronization module determines that synchronization
is lost. It also generates an interrupt if the S3_LS_IE bit
is set in the SMR. The L64724 clears the S3_LS bit to 0
after a reset or a Group 2 (STS) read.
Stage 3 Synchronization Flag
The L64724 sets the S3_S bit when the Descrambler
synchronization module acquires synchronization. The
L64724 also generates an interrupt if the S3_S_IE bit is
S3_LS
VBER
S2_LS
0
1
0
1
D4
STS[7:0]
Definition
VMDC2 period not reached
VMDC2 period reached
Definition
Stage 3 Synchronization status
unchanged
Loss of Stage 3 Synchronization
detected
S2_S
D3
S1_LS
D2
S1_S
D1
Reserved
D0
7
6
5