L64724 LSI Logic Corporation, L64724 Datasheet - Page 103

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.44 Serial Interface to Tuner, Data, and Control
(Group 4: APR 59 to 62)
These registers are used to communicate on a serial bus to the tuner
using the XCTR[3:0] output pins. Both the host microprocessor and the
on-chip microcontroller can write to the registers.
A 390 KHz SCLK for the serial protocol is generated on-chip by dividing
the crystal clock (assumed to be 15 MHz) by 38. The SCLK signal is
output on the XCTR[1] pin. SDATA for the serial protocol is output on the
XCTR[0] pin.
When the Serial_C bit is a 1, a 3-wire protocol is used to transmit the
serialized data on XCTR[2:0], with XCTR[2] acting as the ENABLE
signal.
Read/Write: R/W
TXSD[6:0]
STXD[7:0]
Group 4: Configuration Registers
APR
59
60
61
62
Serial_B
D7
Serial Transmission Start Data
When the APR 59 register is written, the on-chip
serializer module generates the START condition on the
SCLK (XCTR[1]) and SDATA (XCTR[0]) pins, serializes
and transmits the address in TXSD[7:1] (MSB first), and
appends a R/W bit of 0 to indicate a write cycle to the
tuner.
Serial Transmission Data
When the APR 60 register is written, the STXD[7:0] data
is serialized and transmitted as the next data byte. The
first bit sent serially is the MSB, bit 7. This register is
buffered by the serializer so that a second 8-bit data byte
can be loaded into STXD before waiting for the previous
byte to be serialized. For a detailed description of the
cycles, please refer to Appendix C “Programming the
Serializer.”
Serial Transmission Start Data, TXSD[6:0]
D6
Serial_C[1:0]
Serial Transmission End Data, TXED[7:0]
Serial Transmission Data, STXD[7:0]
D5
D4
SPI_M[3:0]
D1
Reserved
Serial_A
D0
[7:1]
[7:0]
3-73