L64724 LSI Logic Corporation, L64724 Datasheet - Page 209

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

D[0]
D[1]
D[1]
D[1]
Figure A.3
Start Condition: The master (drives D[0]) indicates the start of a cycle by pulling D[1] LOW when D[0] is HIGH.
Stop Condition: The master (drives D[0]) indicates the end of a cycle by releasing D[1] HIGH when D[0] is HIGH.
Data Transfer: All data changes on the D[1] line occur only when clock is LOW, except for the special cases outlined above to
Acknowledge: The receiver always generates the acknowledge. In the case of a single read, the master-receiver does not generate
Master-Transmitter, Slave-Receiver (Master transmits slave address)
Master-Transmitter, Slave-Receiver (Master transmits slave address)
Start Condition
Master-Transmitter, Slave-Receiver (Master transmits slave address)
bit7
bit7
bit7
Serial Bus Write/Read Cycle Overview
bit6
bit6
bit6
indicate Start/Stop cycles.
an ACK so that it can generate the Stop condition (as indicated above).
bit5
bit5
bit5
bit4
bit4
bit4
bit3
bit3
bit3
bit2
bit2
bit2
bit1
bit1
bit1
Read Cycle(burst)
Single-Read Cycle
R/W
R/W
R/W
Write Cycle
ACK Cycle: Slave
ACK Cycle: Slave
ACK Cycle: Slave
bit7
bit7
bit7
Master-Receiver, Slave-Transmitter (Slave transmits data to master)
Master-Receiver, Slave-Transmitter (Slave transmits data to master)
Master-Transmitter, Slave-Receiver (Master transmits data to slave)
bit6
bit6
bit6
bit5
bit5
bit5
bit4
bit4
bit4
bit3
bit3
bit3
bit2
bit2
bit2
bit1
bit1
bit1
ACK Cycle: Master
bit0
bit0
bit0
ACK Cycle: Mas ter
ACK Cycle: Slave
Stop Condition
Stop Condition
bit7