L64724 LSI Logic Corporation, L64724 Datasheet - Page 244

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

B.4 QPSK Demodulator and FEC Configuration Example:
B-30
Low Data Rates
This section contains an example of how to configure the QPSK
Demodulator section of the L64724 through its microcontroller interface.
This example configuration is optimized for fixed rate operation with the
following parameters:
Transmission Rate:
ADC Sampling Frequency
Xtal OSC
ADC
DC Offset Control
Viterbi Rate
E
Model
The registers for this example are configured as shown in the following
subsections. See
register settings.
Group 4, APR 0 – Set to 0x81.
Set bit D7 to 1 and clear bit D6 to 0. Based on Section 4.2, set the
PLL_N[5:0] field to 0x01 (PCLK = 60 MHz.)
Group 4, APR 1 – Set to 0x04.
Clear bits D7 and D6 to 0. Based on section 4.2, set the PLL_S[5:0] bits
to 0x04 (PCLK = 60 MHz.)
Group 4, APR 2 – Set to 0x01.
Set the IMQ bit (D7) to either 1 or 0, clear the DVB_DSS bit (D6) bit
to 0 for DVB, and clear the QB bit (D5) to 0 for QPSK. Based on
Table 4.2, set the PLL_T[4:0] bits to 0x01.
L64724 Application Notes
b
/N
o
Table
B.14, on
4.0 Mbit/s (2.0 Mbaud)
60 MHz
15.00 MHz
Input: 1.0 V p-to-p
Used
1/2
4.0 dB
DVB
page
B-45, for a summary of the