L64724 LSI Logic Corporation, L64724 Datasheet - Page 68

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.2 PLL Parameter S (Group 4: APR 1)
3.6.3 PLL Parameter T, Demodulator and Symbol Select
3-38
(Group 4: APR 2)
PLL_N
The PLL Configuration Parameter S (PLL_S[5:0]) configures the PLL
module for clock synthesis.
Read/Write: R/W
Reserved
PLL_S
The PLL Configuration Parameter T (PLL_T[4:0]) configures the PLL
module for clock synthesis. This register also contains bits to configure
the demodulator and select the symbol format.
Read/Write: R/W
IMQ
L64724 Registers
APR
APR
1
2
IMQ
D7
D7
Reserved
DVB_DSS
PLL Configuration Parameter N
PLL_N[5:0] is one of four parameters (PLL_S, PLL_N,
PLL_T, and PLL_M) that you must set to configure the
PLL module for clock synthesis. For more information,
see
Reserved
The Reserved bits are internal test bits that must be
cleared to 0.
PLL Configuration Parameter S
PLL_S[5:0] is one of four parameters (PLL_S, PLL_N,
PLL_T, and PLL_M) that you must set to configure the
PLL module for clock synthesis. For more information see
Section 4.2, “PLL Clock Generation.”
(I, -Q) Symbol Format
The IMQ bit indicates the format of the incoming symbol
stream. The IMQ_EN bit (APR 15, D3) must be cleared
D6
D6
Section 4.2, “PLL Clock Generation,” page 4-3.
D5
QB
D5
D4
PLL_S[5:0]
PLL_T[4:0]
D0
D0
[5:0]
[7:6]
[5:0]
7