L64724 LSI Logic Corporation, L64724 Datasheet - Page 97

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.40 Clock Loop Configuration Register (Group 4: APR 53)
Read/Write: R/W
APR
53
CLK_SWP_
SWAP
D7
CLK_ERROR
CLK_BIAS
This register contains the various control bits that are used to configure
the Clock Synchronizer Loop logic.
CLK_SWP_SWAP
CLK_ERROR_SWAP
CLK_AUTO_SWP
Group 4: Configuration Registers
_SWAP
D6
AUTO_
CLK_
SWP
D5
Clock Loop Bias
Program the CLK_BIAS registers to set the value for the
bias parameter within the clock recovery loop.
Swap Clock Sweep Direction
Set the CLK_SWP_SWAP bit to control whether the
Clock acquisition frequency sweep direction is normal or
reversed. It should be toggled whenever the clock sweep
reaches its limit without achieving clock lock.
Swap Timing Error Detector
Set the CLK_ERROR_SWAP bit to control the polarity of
the timing error detector. When the bit is set to 1, the
polarity of the detector output is inverted.
Automatic Timing Sweep Control
Set the CLK_AUTO_SWP bit to enable automatic control
of the timing sweep mechanism. When set to 1, the
control of the sweep is handled internally. See
CLK_SWP_SWAP
CLK_ERROR_
Set to 1
D4
SWAP
0
1
0
1
AGC_CLK_
SEL
D3
Error Detector Output
Normal
Inverted
Sweep Operation
Increasing Frequency
Decreasing Frequency
Reserved
D2
CLK_OPEN
D1
CLK_SW
D0
[30:0]
3-67
7
6
5