MT312 Zarlink Semiconductor, MT312 Datasheet - Page 18

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

2.5.1
Where the symbol rate and/or the Viterbi code rate are unknown, the MT312 can be programmed to search for
QPSK/BPSK signals. The user should define the range(s) over which the search is required. The MT312 will then
locate and track any signal detected. Failure to find a QPSK signal in the specified frequency and specified symbol
rate ranges will be indicated by interrupts (see section 7.2 “QPSK Demodulator Read Registers” on page 45).
MT312 will carry on searching these ranges after issuing these interrupts. When the MT312 has locked onto a
signal, the symbol rate in MS/s may be read from the MONITOR registers. The Viterbi code rate may be read from
the FEC_STATUS register. This search facility is primarily for the initial installation of a set top box.
2.6
The MT312 has the capability to send and receive DiSEqC™ messages. Eight registers are provided to store a
message for transmission and a further eight registers are provided to store a received message. The received
bytes have a parity bit and a parity error bit in addition to the eight data bits. These additional bits are read out in
sequence following the data bits, so two byte reads are required for each data byte.
2.6.1
The sequence of events to send a message are as follows:
1. Load the required message bytes into the DiSEqC™ instruction register 36, see page 34. Sequential writes to
2. Load the number of bytes (less one) in the DiSEqC™ instruction in the register DISEQC_MODE[5:3], see
3. Set DISEQC_MODE[2:0] = 4 to command the MT312 to encode the data and transmit the message.
4. Reset DISEQC_MODE[2:0] to either 0 or 1 depending on previous setting of 22kHz off or on. The data loaded
the same register are achieved by setting the Inhibit Auto Incrementing (IAI) bit 7 in RADD, the register address
byte.
page 33.
into the DISEQC_INSTR register is retained, so that if the same message is to be repeated, stage 1 above can
be omitted.
High level input/output
(MS/s, MHz)
Low level register read/write
DiSEqC™ Transmit and Receive Messages
Symbol Rate and Code Rate Search Mode
DiSEqC™ transmitting messages
Command
Control
Driven
Figure 11 - MT312 control structure
Zarlink Semiconductor Inc.
registers
MT312
MT312
format
18
State Machine
Acquisition/
Track
Design Manual
QPSK