MT312 Zarlink Semiconductor, MT312 Datasheet - Page 74

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

11.2.43
bit-7-6:
bit-5-4:
bit-3-0:
11.2.44
PROG SYNC (98)
PROG SYNC[7:0]
11.2.45
AFC SEAR TH (99)
AFC SEAR TH[7:0]
11.2.46
CSACC DIFF TH (100)
CSACC DIFF TH[7:0]
11.2.47
bit-7:
bit-6:
bit-5:
bit-4-0:
QPSK LK CT
BA SETUP
NAME
NAME
Byte Align Set up register 95 (R/W)
Program Synchronising Byte register 98 (R/W)
AFC Frequency Search Threshold register 99 (R/W)
Accumulator Differential Threshold register 100 (R/W)
QPSK Lock Control register 101 (R/W)
ADR
ADR
BA FSM[1:0]
MA MV[2:0] + 5 =
BA UNLK[3:0] +3 =
CS L LK
TS L LK
ACC CK
NUM_PLD INT[4:0]
101
95
bit-7
BA FSM[1:0]
CS L LK
bit-7
Default value
Default value
Default value
If FEC_SETUP[2] is high, use the PROG SYNC value to synchronise MPEG
data packets.
bit-6
TS L LK
bit-6
bit-5
Zarlink Semiconductor Inc.
BA MV[1:0]
MT312
Byte Align FSM mode.
Byte Align majority voting.
Number of bad sync words to unlock the Byte Align. The
default register value of 4 is equivalent to 7 bad sync words.
71 dec.
35 dec.
32 dec.
High = Use CS long lock.
High = Use TS long lock.
High = Disable Accumulator check option.
Maximum value allowed is 29.
ACC CK
bit-4
74
bit-5
bit-3
bit-
4
47 hex.
23 hex.
20 hex.
NUM_PLD INT[4:0]
bit-2
BA UNLK[3:0]
bit-
3
bit-
bit-1
2
bit-
1
bit-0
bit-
0
Design Manual
R/W
R/W
hex
Def
hex
Def
04
D4