MT312 Zarlink Semiconductor, MT312 Datasheet - Page 23

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

Figure 13 - Initialization sequence in DVB mode.
Program tuner via GPP in 'pass through mode'
Release Reset state to start signal capture
Reset MT312 to default register settings
Initialise register: reg 49 = 50 (32hex);
Reg 24 = 128 (80hex) DEFAULT state
Reg 23 = 27 (1Bhex) DEFAULT state
open port with Reg 20 = 64 (40hex)
Set SYS_CLK = 2*Xtal*PLL_RATIO
send TUNER DATA via 2-wire bus.
Set DISEQQC_RATIO (if required)
Enable MT312: Program CONFIG
eg V_IQ swap not set, CR = 3/4:
e.g. Horizontal with 22kHz on:
Reg 26 = 0 DEFAULT state
Zarlink Semiconductor Inc.
close port with Reg 20 = 0
Signal input - symbol rate
Set AGC_SL (if required)
Reg 127 = 140 (8Chex)
eg DVB: roll-off = 0.35:
Reg21 = 128 (80hex)
Reg 22 = 65 (41hex)
Reg 25 = 4 (4hex)
DISEQC_MODE
Viterbi code rate
eg 27.5 MS/s:
QPSK control
MT312
Reg 27 = 1
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