MT312 Zarlink Semiconductor, MT312 Datasheet - Page 50

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

8.1.2
If more than one bit is enabled then the logical-OR combination of the selected status signals will appear on the
STATUS pin 52.
bit-7-4:
bit-3:
bit-2:
bit-1:
bit-0:
8.1.3
bit-7:
bit-6:
bit-5:
bit-4:
bit-3:
bit-2:
bits1-0:
FEC_STAT_EN
FEC_SETUP
NAME
NAME
FEC_STATUS output enable register 33 (R/W)
FEC setup register 97 (R/W)
MOCLK_RATIO[3:0] MPEG clock ratio - 6. i.e. range is from 6 to 21
DS_lock
BA_lock
VIT_lock
BER_tog
When MANUAL_MOCLK (“Output data control register 96 (R/W)” on page 62) is low then:
ENCL_KO
DIS_RS
DIS_VIT
EN_PRS
DIS_SR
When MANUAL MOCLK (register 96 bit 7) is high then:
DIS_SR
DIS_DS
DS_LK[1:0] + 2
ADR
97
ADR bit-7 bit-6 bit-5 bit-4
33
DIS_SR ENCL_KO DIS_DS DIS_RS DIS_VIT EN_PRS DS_LK[1:0] R/W
bit-7
MOCLK_RATIO[3:0]
Synchronising Byte register 98 (R/W)” on page 74).
= Number of bytes for de-scrambler to lose lock. The default register value of 3 is
equivalent to 5 bad sync words.
High = De-scrambler lock
High = Byte Align lock
High = Viterbi lock
High = BER toggle. This bit enables an audio frequency signal to be output on the
STATUS pin to indicate BER during dish alignment, see section 2.4.1.1 “Viterbi
error count coarse indication” on page 13. The frequency of the signal is controlled
by VIT_MAXERR register (94), see page 73.
High = Disable use of symbol rate for MOCLK generation.
Low = Use symbol rate for MOCLK generation.
High = Use external MICLK (pin 14) signal for MOCLK.
Low = Manually set MOCLK period from MOCLK_RATIO (“FEC_STATUS output
enable register 33 (R/W)” on page 50).
High = Enable clock out for test purposes.
High = Disable de-scrambler.
High = Disable Reed-Solomon decoder.
High = Disable Viterbi (Viterbi by pass mode)
High = Enable programmed synchronisation byte in register 98 (see “Program
see section 10.1.3 “MANUAL MOCLK = 1 and DIS_SR = 0” on page 56.
bit-6
Zarlink Semiconductor Inc.
bit-5
MT312
DS_lock BA_lock VIT_lock BER_tog R/W
bit-3
50
bit-4
bit-2
bit-3
bit-1
bit-2
bit-0
bit-1 bit-0
Design Manual
hex
Def
14
hex
Def
03