MT312 Zarlink Semiconductor, MT312 Datasheet - Page 21

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

4.2
CONFIG[bits 7-0]: This register is for setting up the MT312. It must be loaded first before any other register. It can
only be reset to the default value by the RESET pin being pulled low.
CONFIG[bit-7]:
CONFIG[bits 6-5]: DSS_B
If both DSS_A and DSS_B are set high, the MT312 will search for the code rate in DSS mode. If either of the
DSS_A or DSS_B are set high, the symbol rate is automatically set to 20MS/s and SYM_RATE registers (23 & 24)
are ignored. The matched filter root-raised-cosine roll-off is set to 0.20 and bit-0 of QPSK_CTRL (26) is ignored.
Also, any code rate programmed into VIT_MODE register (25) and VIT_SETUP register (86) will be ignored.
Also in DSS mode, the TS_SW_RATE register (50) must be set to 20, see “Timing Synchronisation Sweep Rate
register 50 (R/W)” on page 67.
CONFIG[bit-4]:
CONFIG[bits3-2]:
CONFIG[bit-1]:
CONFIG[bit-0]:
e.g. For a crystal frequency of 10MHz, a system clock frequency of 60MHz, the PLL ratio will be 6, requiring the
PLL_FACTOR[1:0] = 2.
For QPSK reception and ADC internal, the MT312 is enabled by writing 88hex to register 127.
MT312 computes the System clock frequency using bit-3 to bit-1 above. This frequency is used internally for
computing parameters needed for acquiring the QPSK signal.
It is possible to use a crystal frequency other than 10 or 15 MHz. As an example, if the crystal frequency is
10.25MHz and the PLL multiplication factor is 6. Then bit-3 is set to 1 and bit-2 to 0. Bit-1 may be given an arbitrary
value (0 or 1). The external software must compute the system clock frequency and load this value (multiplied by 2)
to the SYS_CLK register (address 34). In the above example, the system clock frequency is 61.5 MHz and hence
the value 123 has to be loaded into SYS_CLK register.
The QPSK demodulator checks the SYS_CLK register and if this is non-zero, it uses the contents of this as the
system clock frequency, for internal calculations mentioned above. If this register is zero (which is the default
setting), QPSK demodulator works out the system clock frequency from bits-3- bit-1 of the CONFIG register
assuming that the crystal frequency is either 10 or 15 MHz, as defined by bit-1.
The configuration register (127)
312_EN
BPSK High = BPSK
PLL_FACTOR[1:0]:
bit-3
0
0
1
1
CRYS15
ADCEXT
0
0
1
1
Low = QPSK
High = MT312 enable.
Low = MT312 disable to save power.
Low = 10MHz crystal.
High = ADC external.
Low = ADC internal.
DSS_A
bit-2
0
1
0
1
High = 15MHz crystal.
0
1
0
1
Zarlink Semiconductor Inc.
MT312
Mode
DVB mode
DSS mode 1 - code rate 2/3
DSS mode 2 - code rate 6/7
DSS Code Rate search
Multiplication factor
3
4
6
9
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Design Manual