MT312 Zarlink Semiconductor, MT312 Datasheet - Page 9

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

Overview
The MT312 is a QPSK/BPSK 1 to 45MS/s demodulator and channel decoder for digital satellite television
transmissions compliant to both DVB-S and DSS standards and other systems, such as LMDS, that use the same
architecture.
A Command Driven Control (CDC) system is provided making the MT312 very simple to program. After the tuner
has been programmed to the required frequency to acquire a DVB transmission, the MT312 requires a minimum of
five registers to be written.
The MT312 provides a monitor of bit error rate after the QPSK module and also after the Viterbi module. For
receiver installation, a high speed scan or 'blind search' mode is available. This allows all signals from a given
satellite to be evaluated for frequency, symbol rate and convolutional coding scheme. The phase of the IQ signals
can be automatically determined.
Full DiSEqC™ v2.2 is provided for both writing and reading DiSEqC™ messages. Storage in registers for up to
eight data bytes sent and eight data bytes received is provided.
Additional Features
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Demodulator
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Viterbi
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2-wire bus microprocessor interface.
All-digital clock and carrier recovery.
On-chip PLL clock generation using a low cost
10 to 15MHz crystal.
3.3V operation.
80 pin MQFP package.
Low external component count.
Commercial temperature range 0 to 70°C.
BPSK or QPSK programmable.
Optional fast acquisition mode for low symbol
rates.
Programmable decoder rates 1/2, 2/3, 3/4, 5/6,
6/7, 7/8.
Automatic spectrum resolution of IQ phase.
Constraint length k=7.
Trace back depth 128.
Extensive SNR and BER monitors.
Q I/P
I I/P
Dual ADC
Ccontrol
Analog
AGC
De-rotator
Figure 1 - MT312 functional block diagram
Clock Generation
Zarlink Semiconductor Inc.
Decimation
Filtering
MT312
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De-Interleaver
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Reed-Solomon
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De-Scrambler
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Outputs
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Application Support
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Compliant with DVB and DSS standards.
(204, 188) for DVB and (146,130) for DSS.
Reed-Solomon bit-error-rate monitor to indicate
Viterbi performance.
EBU specification de-scrambler for DVB mode.
MPEG transport parallel & serial output.
MPEG clock input for external synchronising of
MPEG data output.
Integrated MPEG2 TEI bit processing for DVB only.
Channel decoder system evaluation board.
Windows based evaluation software.
ANSI-C generic software.
Timing recovery
Phase recovery
Acquisition
Matched filter
Control
2-wire Bus
Interface
DVB
DSS
FEC
Design Manual
Bus I/O
Packets
MPEG/
DSS