MT312 Zarlink Semiconductor, MT312 Datasheet - Page 31

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

5.5
5.5.1
LNB_FREQ[15:0] Frequency offset in steps of 1·953125kHz (MHz/512). This is a 2's complement 16 bit number.
e.g. a hex value of F680 (= -2432) represents an offset of -4.75MHz.
Once the chip is in lock, these two registers provide a measurement of the frequency of the signal at the input to
MT312. Ideally, this frequency is zero. Due to LNB frequency uncertainty this frequency may take a positive or
negative value. The analogue front-end may then be re-tuned to bring this offset close to zero. Note that MT312
indicates the frequency location of the QPSK spectrum with respect to zero frequency. The direction in which the
synthesiser frequency has to be stepped depends on the design of the analogue front-end. Also note that in many
instances it will not be necessary to re-tune even when there is a relatively large frequency offset. This is because
MT312 compensates for this frequency offset before it demodulates the signal. Re-tune only if a substantial part of
the QPSK spectrum is affected by the base-band filter which precedes MT312. This will be the case only for symbol
rates which are close to the maximum symbol rate supported by the above mentioned filters.
When MT312 locks, part of the frequency offset is taken up by the frequency compensation mixer and part by the
carrier synchroniser. LNB_FREQ gives only the value in the frequency compensation mixer. Over a short period of
about one second after lock, the carrier synchroniser will transfer all the frequency compensation to the mixer.
Hence the LNB_FREQ reading will have an error less than ±5% of the symbol rate during this short period after
lock. If an accurate frequency reading is needed immediately after lock, the calculation given in section on
FREQ_ERR2 has to be performed by external software.
5.5.2
FREQ_ERR1[23:0] is the ratio of frequency compensation mixer offset to system clock x 2
number.
For most purposes the LS byte can be ignored hence the alternative definition is more useful: FREQ_ERR1[23:8] is
the ratio of frequency compensation mixer offset to system clock x 2
FREQ_ERR2 [16:0] is the ratio of carrier synchroniser offset to symbol rate x 2
value drops to near zero within about a second of signal lock. To obtain an accurate value for the frequency offset at
LNB_FREQ H
LNB_FREQ L
FREQ_ERR2 H
FREQ_ERR1 M
FREQ_ERR1 H
FREQ_ERR2 L
FREQ_ERR1 L
NAME
NAME
Tuner Control Read Registers
NAME
Measured LNB frequency error registers 7 - 8 (R)
Frequency error 1 and 2 registers 111 - 115 (R)
ADR
07
08
ADR
ADR
114
115
111
112
113
bit-7
LNB_FREQ[15:8] Measured LNB frequency error (high byte)
LNB_FREQ[7:0] Measured LNB frequency error (low byte)
bit-7
FREQ_ERR1[15:8] Input frequency error coarse (middle byte)
bit-7
FREQ_ERR1[23:16] Input frequency error coarse (high byte)
FREQ_ERR2[15:8] Input frequency error fine (high byte)
FREQ_ERR2[7:0] Input frequency error fine (low byte)
FREQ_ERR1[7:0] Input frequency error coarse (low byte)
bit-6
bit-6
bit-6
bit-5
bit-5
bit-5
Zarlink Semiconductor Inc.
bit-4
bit-4
MT312
bit-4
31
bit-3
bit-3
bit-3
bit-2
bit-2
16
bit-2
. A 16-bit signed number.
bit-1
bit-1
bit-1
8
. It is a 16-bit signed number. This
bit-0
bit-0
bit-0
R
R
R
R
24
R
R
R
. It is a 24-bit signed
Def hex
Def hex
Design Manual
00
00
00
00
Def hex
00
00
00