MT312 Zarlink Semiconductor, MT312 Datasheet - Page 24

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

4.4
Spectral inversion of the QPSK signal can be caused by the transmitter or the receiver front-end. In the latter case,
this could happen due to the way I-Q conversion is carried out or because the I and Q connections are swapped
between the I-Q converter and the MT312. If spectral inversion is caused by the receiver front-end, then this must
be removed by swapping I and Q (within MT312) before QPSK demodulation, by setting the Q_IQ_SP bit-6 of
QPSK control register 26 (R/W) to 1. If no spectral inversion is caused by the receiver front-end design, then bit-6 of
QPSK_CTRL should be set to zero.
If the transmitted signal is known to be spectrally inverted, then V_IQ_SP bit-6 of the Viterbi mode register 25 (R/W)
may be set to 1, or if the spectral inversion status of the transmitted signal is not known, then the AUT_IQ bit-7 of
the same register may be set to 1 to allow the MT312 to determine the spectral inversion automatically.
4.5
Also see “The configuration register (127)” on page 21
4.5.1
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RESET
bit-7:
bit-6:
bit-5:
bit-4:
bit-3:
bit-2:
bit-1:
bit-0:
NAME
Writing a one to these register locations generates a reset pulse three crystal clock periods wide.
The register automatically resets to zero after use.
A full reset resets the registers to their default values.
A partial reset does not reset the registers to their default values.
Spectral inversion
Read/write registers
Reset register 21 (R/W)
FR_312
PR_312
FR_QP
PR_QP
FR_VIT
PR_VIT
PR_BA
PR_DS
ADR
21
FR_312 PR_312 FR_QP
bit-7
High = Full reset of MT312 device.
High = Partial reset of MT312 device.
High = Full reset of QPSK block.
High = Partial reset of QPSK block.
High = Full reset of Viterbi block.
High = Partial reset of Viterbi block.
High = Partial reset of Byte Align block.
High = Partial reset of De-scrambler block.
bit-6
bit-5
Zarlink Semiconductor Inc.
PR_QP
bit-4
MT312
24
FR_VIT
bit-3
PR_VIT
bit-2
PR_BA
bit-1
PR_DS R/W
bit-0
Design Manual
Def
hex
00