MT312 Zarlink Semiconductor, MT312 Datasheet - Page 48

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

7.2.3
SYM_RAT_OP[15:0] These two bytes contain a positive number that is inversely proportional to the symbol rate.
The decimation ratio index must also be read from the MONITOR register bits B[7:5] and divided by 32 to normalise
the result.
Where:
7.2.4
For details, see MON_CTRL register (103) on page 63.
MON_CTRL[3:0] = 0:
This is a snapshot of two I and Q samples (of the same symbol) after carrier synchroniser. This information can be
used to produce a scatter diagram. Keep reading these continuously and mark these as points on a 2-D I-Q plane
to get a scatter diagram.
MON_CTRL[3:0] = 1:
This will give the amount of DC offset in the I and Q inputs from the ADC compensated by the QPSK. Each of these
is a two's complement number. If the 6-bit ADC range is taken to be in the scale -32 to 31, then it is necessary
divide DC_OFFSET_I by 16, to bring it to the same scale as the ADC. For example, if we get the DC_OFFSET_I as
"11111101", the corresponding two's complement number is -3. However, the actual offset with respect to the ADC
scale of [-32, 31] is actually -3/16. The same applies to DC_OFFSET_Q.
MON_CTRL[3:0] = 3:
When the QPSK demodulator is in lock following a symbol rate search, the locked symbol rate may be read from
the MONITOR register. Then:
The accuracy of this reading is within ±0.25% of the actual symbol rate. Note that the channel with this symbol rate
can be subsequently re-acquired without a search by programming the 14 MSBs of the above read-out (discarding
the two LSBs) as the 14 LSBs of the 16-bit SYM_RATE register (23,24), see page 39.
MONITOR_H
SYM_RAT_OP_H
SYM_RAT_OP_L
MONITOR_L
NAME
NAME
Symbol Rate Output registers 116 - 117 (R)
Monitor registers 123 - 124 (R)
Rs = symbol rate in MS/s
PLL_CLK = PLL clock frequency in MHz
SYM_RAT_OP = value of registers 116 and 117.
DEC_RATIO = MONITOR_H[7:5] when MON_CTRL[2:0] = 5.
Rs
=
ADR
123
124
----------------------------------------------------------- -
SYM_RAT_OP
PLL_CLK 8192
ADR
116
117
bit-7
bit-7
MONITOR_H = CS_SYM_I and MONITOR_L = CS_SYM_Q.
MONITOR_H = DC_OFFSET_I and MONITOR_L = DC_OFFSET_Q.
MONITOR_H = MS/s OP_H and MONITOR_L = MS/s OP_L.
Symbol Rate = MONITOR[15:0]/1024.
+
SYM_RAT_OP[15:8] Symbol Rate Output (high byte)
bit-6
SYM_RAT_OP[7:0] Symbol Rate Output (low byte)
8192
MONITOR[15:8] Monitor (high byte)
bit-6
MONITOR[7:0] Monitor (low byte)
bit-5
2
–
DEC_RATIO
bit-5
Zarlink Semiconductor Inc.
bit-4
MT312
bit-4
48
bit-3
bit-3
bit-2
bit-2
bit-1
bit-1
bit-0
bit-0
R
R
R
R
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Design Manual
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