MT312 Zarlink Semiconductor, MT312 Datasheet - Page 45

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

7.2
7.2.1
The majority of these interrupts are for diagnostic purposes and generally not useful in normal operation, unless
otherwise indicated.
bit-7:
bit-6:
bit-5:
bit-4:
bit-3:
bit-2:
bit-1:
bit-0:
Reading an interrupt register resets that register.
After the QPSK demodulator achieves Carrier and Timing Lock, from now on referred to as QPSK CT Lock, it waits
some time for the FEC to confirm this lock. When the FEC locks, the QPSK enters QPSK Lock state. The time
QPSK waits for the FEC to gain lock is programmable via register 81 (see Section 11.2.31 “FEC Lock Time register
81 (R/W)” on page 71). If the FEC does not achieve lock during this period (very unlikely), then MT312 drops its
QPSK CT Lock status and resumes search for another QPSK signal.
bit-7:
bit-6:
bit-5:
bit-4:
bit-3:
bit-2:
bit-1:
bit-0:
Reading an Interrupt register resets that register.
QPSK_INT_M
QPSK_INT_H
NAME
NAME
QPSK Demodulator Read Registers
QPSK Interrupt registers 0 - 2 (R)
High = QPSK Carrier and Timing LOCK - important indicator.
High = QPSK Carrier and Timing UNLOCK
High = QPSK_LOCK - important indicator.
High = QPSK_UNLOCK
High = QPSK Timing LOCK
High = QPSK Timing UNLOCK
High = QPSK Carrier LOCK
High = QPSK_FE_AGC_LOCK
High = QPSK Digital Internal AGC LOCK
High = QPSK_FR_LOCK
High = QPSK_FR_UNLOCK
High = QPSK calculation complete
High = QPSK_TS_MAX
High = QPSK_CS_MAX
High = QPSK Carrier UNLOCK
High = QPSK Digital Internal AGC UNLOCK
ADR
ADR
01
00
bit-7
bit-7
QPSK_INT[15:8] Interrupt QPSK (middle byte)
QPSK_INT[23:16] interrupt QPSK (high byte)
bit-6
bit-6
bit-5
bit-5
Zarlink Semiconductor Inc.
bit-4
bit-4
MT312
45
bit-3
bit-3
bit-2
bit-2
bit-1
bit-1
bit-0
bit-0
R
R
hex
Def
hex
Def
00
00
Design Manual