MT312 Zarlink Semiconductor, MT312 Datasheet - Page 43

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

7.1.5
When the bits of these three registers are set high, they enable an event to generate an interrupt on the IRQ pin 57.
All interrupts may be enabled together. These registers do not affect the indication of events in the read
registers 0 - 3.
bit-7:
bit-6:
bit-5:
bit-4:
bit-3:
bit-2:
bit-1:
bit-0:
bit-7:
bit-6:
bit-5:
bit-4:
bit-3:
bit-2:
bit-1:
bit-0:
IE_QPSK_H
IE_QPSK_M
NAME
NAME
QPSK interrupt output enable registers 28 - 30 (R/W)
High = Enable QPSK_CT_LOCK indication on interrupt pin.
High = Enable QPSK_CT_UNLOCK indication on interrupt pin.
High = Enable QPSK_LOCK indication on interrupt pin.
High = Enable QPSK_UNLOCK indication on interrupt pin.
High = Enable QPSK_TS_LOCK indication on interrupt pin.
High = Enable QPSK_TS_UNLOCK indication on interrupt pin.
High = Enable QPSK_CS_LOCK indication on interrupt pin
High = Enable QPSK_CS_UNLOCK indication on interrupt pin.
High = Enable QPSK_FE_AGC_LOCK indication on interrupt pin.
High = Enable QPSK_TS_AGC_LOCK indication on interrupt pin.
High = Enable QPSK_TS_AGC_UNLOCK indication on interrupt pin.
High = Enable QPSK_FR_LOCK indication on interrupt pin.
High = Enable QPSK_FR_UNLOCK indication on interrupt pin.
High = Enable QPSK calculation complete indication on interrupt pin.
High = Enable QPSK_TS_MAX indication on interrupt pin.
High = Enable QPSK_CS_MAX indication on interrupt pin.
ADR
ADR
28
29
bit-7
bit-7
IE_QPSK[15:8] Interrupt enable QPSK (middle byte)
IE_QPSK[23:16] Interrupt enable QPSK (high byte)
bit-6
bit-6
bit-5
bit-5
Zarlink Semiconductor Inc.
bit-4
bit-4
MT312
bit-3
bit-3
43
bit-2
bit-2
bit-1
bit-1
bit-0
bit-0
R/W
R/W
hex
Def
Def
hex
00
00
Design Manual