MT312 Zarlink Semiconductor, MT312 Datasheet - Page 33

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

A 'zero' comprises 22kHz on for 1ms then off for 0.5ms. A 'one' comprises 22kHz on for 0.5ms then off for 1ms. The
ninth bit is an odd parity bit.
6.2
6.2.1
bit-7:
bit-6:
bits5-3:
bits2-0:
Note:
DISEQC_MODE
DiSEqC™ control read/write registers
NAME
DISEQC mode control register 22 (R/W)
HV H/V polarisation control:
Number of bytes in DiSEqC™ instruction minus 1 to output on the DISEQC[0] pin, i.e. if the message
DISEQC mode:
Reserved.
The DISEQC[1] pin controls the externally generated 13/18V LNB voltage.
contains four bytes, program bits 5-3 with the value three.
for modes 2 and 3, an interrupt is generated 16ms (see FEC interrupt register 3 (R)) after the '0' or '1'
burst. For mode 4, there is a 16ms delay before the message bytes, then an interrupt is generated
16ms after the last message byte has been sent (see FEC interrupt register 3 (R)). The requisite
number of bytes must be pre-loaded into the DISEQC instruction register 36 (R/W) before this bit is set,
see page 34.
ADR
22
Figure 19 - One DiSEqC™ data byte - 0x11 (hex) plus parity bit
Reserved
bit-7
Must be set low.
0:
1:
2:
3:
4:
5-7:
bit-6
HV
High = Horizontal, DISEQC[1] pin = high
Low = Vertical, DISEQC[1] pin = low
Zarlink Semiconductor Inc.
bit-5
instruction length
MT312
22kHz off
22kHz on continuous
Burst mode - on for 12.5ms = '0'
Burst mode - modulated 1:2 for 12.5ms = '1'
Modulated with bytes from DISEQC_INSTR
Reserved.
DISEQC
33
bit-4
bit-3
bit-2
22kHz mode
bit-1
bit-0
R/W
Design Manual
Def hex
00
30