MT312 Zarlink Semiconductor, MT312 Datasheet - Page 64

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

11.0
11.1
SNR_THS_HIGH
CS_SW_RATE_1
CS_SW_RATE_2
CS_SW_RATE_3
TS_AGC_LK_TH
AGC_PWR_SET
TLD_OUTLK_TH
PLD_ACC_TIME
SNR_THS_LOW
CS SW RATE 4
TS_SW_LIM_H
TS_SW_LIM_L
CS_KPROP_H
TS_SW_RATE
CS_KPROP_L
QPSK_SCALE
TLD_INLK_TH
PLD_OUTLK3
PLD_OUTLK2
PLD_OUTLK1
PLD_OUTLK0
SWEEP_PAR
AGC_LK_TH
QPSK_MISC
CS_SW_LIM
CS_KINT_H
CS_KINT_L
PLD_INLK3
PLD_INLK2
PLD_INLK1
PLD_INLK0
TS_LPK_M
AGC_MAX
TS_LPK_L
AGC_INIT
AGC_MIN
FLD_TH
TS_LPK
Name
Read/Write Secondary Register Map
Secondary Registers for Test and De-Bugging
ADR
59_
40
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
NONSNR
Reserved
DAGC_D A_OPEN MIX_D CACC_D FOC_D TSLP_D CSLP_D ADC_FM R/W 00
SW_R_N_MX[1:0]
SW_LIM_SC[1:0]
bit-7
QPSK_SCALE[7:0] QPSK output scale factor for IOUT and QOUT outputs
Reserved
Table 9 - Read/write Secondary Register Map
CS_KP1[2:0]
CS_KI1[2:0]
CS_PLD_MPLEN[3:0]
PLD_OUTLK3[3:0]
TS_KPROPE[3:0]
PLD_INLK3[3:0]_
bit-6
AGC_LK_TH[7:0] Front end AGC lock threshold value
TLD_OUTLK_TH[7:0] TLD threshold when not in lock
TS_AGC_LK_TH[7:0] Fine AGC lock threshold value
SNR_THS_HIGH[7:0] SNR estimator high threshold
SNR_THS_LOW[7:0] SNR estimator low threshold
AGC_MAX[7:0] Front end AGC maximum value
AGC_MIN[7:0] Front end AGC minimum value
TLD_INLK_TH[7:0] TLD threshold when in lock
AGC_PWR_SET[7:0] AGC power initial value
AGC_INIT[7:0] Front end AGC initial value
TS_SW_LIM_H[7:0] TS sweep limit high
PLD_OUTLK2[5:0]
TS_SW_LIM_L[7:0] TS sweep limit low
FLD_TH[7:0] Frequency lock threshold
CS_SW_RATE_1[7:0] CS sweep rate
CS_SW_RATE_2[7:0] CS sweep rate
CS_SW_RATE_3[7:0] CS sweep rate
CS_SW_RATE_4[7:0] CS sweep rate
PLD_INLK2[5:0]
bit-5
TS_SW_RATE[7:0] TS sweep rate
CS SW LIM[7:0] CS sweep limit
TS_NR_SWEEP[2:0]
Zarlink Semiconductor Inc.
CS_KP2[4:0]
CS_KI2[4:0]
TS_KPROPE[11:4]
PLD_OUTLK1[7:0]
PLD_INLK1[7:0]
TS_KINTE[7:0]
bit-4
MT312
64
PLD_OUTLK3[9:4]
PLD_INLK3[9:4]
bit-3
LOSSLOCK_INT_SW[3:0]
CS_KP0[4:0]
CS_KI0[4:0]
PLD_OUTLK2[9:6]
TS_KINTE[11:8]
PLD_INLK2[9:6]
bit-2
CS_NR_SWEEP[2:0]
PLD O LK1 [9:8]
PLD INLK1 [9:8]
bit-1
CS_KP1[4:3]
CS_KI1[4:3]
bit-0
R/W 3B
R/W FF
R/W 00
R/W 0A
R/W 1E
R/W 14
R/W 5A
R/W 46
R/W 1E
R/W 40
R/W 84
R/W 20
R/W 48
R/W 70
R/W 90
R/W 7C
R/W 57
R/W 85
R/W 9B
R/W 12
R/W 96
R/W 51
R/W 3B
R/W 27
R/W 82
R/W 0A
R/W 20
R/W AE
R/W E6
R/W 40
R/W 7E
R/W 01
R/W A0
R/W 68
R/W 1A
R/W 48
R/W 49
Design Manual
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