MT312 Zarlink Semiconductor, MT312 Datasheet - Page 25

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

4.5.2
SYS_CLK[7:0] = System clock frequency * 2 in MHz.
If the reference frequency (a crystal or external clock) is other than 10.000MHz or 15.000MHz the SYS_CLK
register must be programmed to indicate the system clock frequency to the calculation unit. The maximum system
clock frequency allowed is 91MHz.
e.g. for a crystal frequency = 10.111MHz, if the PLL multiplication ratio is 9, the system clock frequency = 91MHz
and SYS_CLK[7:0] = 182 (B6hex).
The system clock frequency is NOT affected by the setting of SYS_CLK[7:0] register. For 10MHz and 15MHz
frequencies, the MT312 calculates the system frequency from bits 3-1 in the CONFIG register (see “The
configuration register (127)” on page 21) and this register may be left at the default of 00.
4.6
4.6.1
ID[7:0]: This register provides an identification number related to the MT312 version
5.0
5.1
If the MT312 is running, to change channel keeping the same signal conditions, it is only necessary to change the
tuner data and possibly the DiSEqC™ data. NO reset is necessary.
5.2
If the MT312 is running, to change channel and symbol rate but not Viterbi coding rate, change the tuner data and
possibly the DiSEqC™ data and symbol rate. NO reset is necessary.
5.3
If the signal parameters are unknown, it is possible to instruct the MT312 to find a digital signal and report the
parameters found. Registers 23 and 24 are programmed with the expected range(s) and the search mode bit
SYM_RATE[bit-15] is set high. A code rate search is forced by programming more than one bit in VIT_MODE (25)
register. The IQ spectrum phase can be automatically determined by setting bit-7 in the Viterbi mode register 25
(R/W).
Note: code rate 6/7 is not searched for in DVB mode.
If a signal with the specified symbol rate range (or ranges) is not found in the frequency range searched, a QPSK
Baud End interrupt (bit-6, QPSK_INT_L (2)) is issued. When the MT312 QPSK section has locked to the signal, this
is indicated in register (6) by QPSK_STAT_H[bit-0] = 1. The symbol rate found can be read from registers (123 -
124) MONITOR, provided the register (103) MON_CTRL = 3. The tolerance of the result is ±0.25%. The 14 MSBs
SYS_CLK
NAME
NAME
ID
Read registers
Simple channel change sequence
Channel change sequence with a new symbol rate
Channel change sequence with search mode
Tuner Control
System clock frequency register 34 (R/W)
Identification register 126 (R)
ADR
126
ADR
34
bit-7
bit-7
SYS_CLK[7:0] - System clock frequency x2 in MHz
bit-6
bit-6
bit-5
bit-5
ID[7:0] Chip identification.
Zarlink Semiconductor Inc.
bit-4
bit-4
MT312
25
bit-3
bit-3
bit-2
bit-2
bit-1
bit-1
bit-0
bit-0
R/W
R
Design Manual
Def hex
Def hex
03
00
.