MT312 Zarlink Semiconductor, MT312 Datasheet - Page 20

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

3.2
4.0
4.1
MT312 will be in the power save mode after a hardware reset. The first command to be written must be to the
CONFIGURATION register at address 127. After loading this register, wait 150µs before writing to the RESET
register. During this wait, the tuner can programmed to the required channel frequency via the General Purpose
Port (register 20). Note that the GPP register occupies the address space before the RESET register. If the AGC
slope control bit of AGC_CTRL(39) or the AGC_REF(41) are to be changed, it is best to write to these registers
after writing to the RESET register. This will allow the front-end AGC loop to settle while the other registers are
being written.
Next write 128 to the RESET register (21) to reset the MT312 state machine and all parameter registers to the
default settings. It is then necessary to change the default setting of register 49 (see 11.2.9, SNR_HIGH threshold
value register 49 (R/W)) to 50 (decimal).
If necessary, other default parameters may need to be changed. These may include:
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To invert MOCLK or BKERR output signals - See Output data control register 96 (R/W)
After this, the LNB controls are defined, in the DISEQC mode control register 22 (R/W).
The signal parameters should then be written to the MT312. The symbol rate (Symbol rate registers 23 - 24 (R/W))
may be specified within ±2% of the required value, absolute precision is not required to achieve successful lock and
tracking. If the symbol rate is unknown, a search mode is available.
Selecting the correct bit of Viterbi mode register 25 (R/W), if known, programs the convolutional code rate. If the
code rate is unknown, some or all of the bits of VIT_MODE may be set to force a search for the code rate.
Finally, the MT312 is given a GO command, register (27) GO =1, to release the state machine and to start the
signal acquisition sequence. This is summarised as an example in Figure 13 Initialization sequence in DVB mode.
Section Title
4.0 MT312 Initialization
5.0 Tuner Control
6.0 DiSEqC Control
7.0 QPSK demodulator
8.0 Forward Error Correction
9.0 Automatic Gain Control
10.0 MPEG Packet Data
Output
Slope of AGC control signal - See AGC control register 39 (R/W) [bit-0] AGC_SL bit
AGC Reference value - See AGC_REF Reference Value register 41 (R/W)
Relative phase the of IQ spectrum - See Viterbi mode register 25 (R/W) [bit-6]
LNB frequency search range, default ±6MHz See FR_LIM frequency limit register 37 (R/W)
For low Baud rates only, set fast frequency acquisition mode - See QPSK control register 26 (R/W) [bit-2] = 1
Register usage overview
Initialization sequence
MT312 Initialization
Table 2 - Register usage overview
Register Addresses
21, 127, 34, 126
20, 37, 38, 7-8, 111-115
22, 35-36, 121-122, 118-120
23-30, 32, 0-2, 4-5, 116-117, 123-124
31, 33, 97, 3, 6, 9-18
39, 41, 19, 108-110
93, 103
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MT312
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Design Manual