MT312 Zarlink Semiconductor, MT312 Datasheet - Page 29

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

5.4
5.4.1
bit-7:
bit-6:
bit-5-3:
If bit-6 = 1, pass-through mode, then:
GPP_CTRL
NAME
Tuner Control Read/Write Registers
General purpose port control register 20 (R/W)
Reserved.
GPP_DIR[2:0] Any bit set high configures the corresponding GPP[2:0] pin as an output
2W_PAS:
ADR
20
Figure 17 - Results of symbol rate and code rate search, DVB or DSS mode
Reserved 2W_PAS
bit-7
Must be set low.
High = 2-wire bus pass-through.
Low = GPP pin I/O direction set by GPP_DIR[2:0].
Any bit set low configures the corresponding GPP[2:0] pin as an input
Mixed use of pins as inputs and outputs is allowed.
GPP_DIR[1:0] are ignored,
bit-2: = Input or output set by GPP_DIR[2] - relating to pin 46.
Pin 45 = DATA2, this is a transparent, bi-directional connection to the primary DATA1.
Pin 44 = CLK2, this is a transparent, bi-directional connection to the primary CLK1.
Read symbol rate from MONITOR registers 123 & 124.
Read code rate from FEC_STATUS[bit-6-4] register 6.
bit-6
Symbol rate = MONITOR_H_L/1024 MS/s
"e.g. if MONITOR_H_L = 0x5820 then the
Program MONITOR to read symbol rate
signal is locked and the code rate = 3/4
symbol rate = 22560/1024 = 22·03125,
bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
eg if FEC_STATUS = 2C hex
GPP_DIR[2:0]
MON_CTRL Reg 103 = 3
i.e. 22.0 MS/s +/-0.25%.
Zarlink Semiconductor Inc.
MT312
29
GPP_PIN[2:0]
R/W
Def hex
20
Design Manual