MT312 Zarlink Semiconductor, MT312 Datasheet - Page 19

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

2.6.2
The MT312 will automatically listen for DiSEqC™ messages 5ms after a message has been transmitted. If a return
message is expected, the DISEQC_MODE[2:0] must be set to zero in order to leave the LNB control signal free for
another DiSEqC™ transmitter to respond. The sequence of events to receive a message are as follows:
1. Enable DISEQC2/GPP2 pin 46 as an input by setting GPP_CTRL register address-20 bit-5 to zero.
2. Enable interrupts if the IRQ pin is being used to interrupt the host processor in DISEQC2_CTRL1 register 121.
3. Monitor DISEQC2_INT register.
4. If bit-3 = 1 and bit-1 = 0, there has been no message received.
5. If a message has been received, bit-0 will be set. If bit-1 is also set the message is complete. DISEQC2_INT
6. Read the received message from DISEQC2_FIFO register 120 by setting the Inhibit Auto Incrementing (IAI)
The user may choose to wait for the end of message indication, before reading the message, if it is known that the
message is not greater than eight bytes. However, if the length of message is not known, the message should be
read out of the FIFO by the host as it is being received. Care must be taken to avoid a FIFO buffer overflow.
DISEQC2_INT register bits-7-4 will indicate how many bytes remain in the FIFO.
3.0
This section describes the sequences of register operations needed to acquire DVB and DSS channels with known
or unknown parameters. Communication with the MT312 is via a standard 2-wire bus and the first byte following the
chip address, in write mode, is the register address (RADD). The register map is organised to group important read
registers at the lowest addresses, then the main control write registers in the next block of addresses. The first
register to be written must be the configuration register, which has been placed at the highest register address,
because it is only written once during the initialization sequence. The CONFIG register can only be reset by the
hardware reset. The MT312 is held in a power saving mode following the hardware reset.
After a hardware reset, the MT312 must be taken out of the power save mode by writing a one to the MSB of the
CONFIG register (see “The configuration register (127)” on page 21). When MT312 is not being used it can be put
back into the power save mode by writing a zero to the MSB of CONFIG.
3.1
All write/read registers take on default values on full software reset, except for the configuration register (127),
which is only reset to the default value by a hardware reset.
register bits-7-4 indicate how many bytes have been received.
bit-7 in RADD, the register address byte and sequentially reading DISEQC2_FIFO for the indicated number of
bytes. Each data byte read requires two 2-wire bus reads. The second or the pair of bytes contains the parity bit
and a parity bit error indicator.
07 - 19, 108 - 117, 123, 124
40, 42 - 49, 50 - 106, 125
MT312 register map overview
MT312 software control
DiSEqC™ receiving messages
20 - 39, 41, 96, 103
107, 118 - 122
Address
00 - 06
126
127
Table 1 - MT312 register map overview
Primary control parameters
Primary signal monitors
Secondary parameters
Secondary monitors
Interrupt and Status
Chip configuration
Chip identification
Zarlink Semiconductor Inc.
Description
MT312
19
write/read
write/read
write/read
Type
read
read
read
read
Design Manual
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