MT312 Zarlink Semiconductor, MT312 Datasheet - Page 62

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

10.5
10.5.1
bit-7:
bit-6:
bit-5:
For a description of how to use these features, see section 10.1 “MPEG clock modes” on page 56.
With MCLKINV = 0, data are clocked out on the positive edge of MOCLK. If MCLKINV = 1, data are clocked out on
the negative edge of MOCLK.
bit-4:
bit-3:
bit-2 -0:
OP_CTRL
NAME
Data output delay (when MCLKINV = 1)
MPEG Packet Data Output Read/Write Registers
Output data control register 96 (R/W)
MANUAL_MOCLK Manual MOCLK mode selection, see register 97 on page 50.
MCLKINV
EN_TEI
BSO
BA_LK[2:0] + 2
BKERIV
ADR
96
MANUAL_MOCLK BKERIV MCLKINV EN_TEI BSO
Parameter
bit-7
packet header byte 2 when the block is flagged as uncorrectable by the
Reed-Solomon decoder. See section 10.2 “Data Output Header Format - DVB” on
page 58. (Not used in DSS).
High = Inverted signal on BKERR output pin.
Low = Normal signal on BKERR output pin.
High = Normal signal on MOCLK output pin.
Low = Inverted signal on MOCLK output pin.
High = Enable automatic setting of transport error indicator (TEI) bit in MPEG
High = Bit serial output of the MPEG data on MDO0 pin.
Low = Parallel output of the MPEG data on MDO[7:0] pins.
= Number of bytes for byte aligner to lock.
The default register value of 3 is equivalent to 5 good sync words.
Figure 23 - MT312 Data Output Timing Diagram
bit-6
Zarlink Semiconductor Inc.
Symbol
MT312
bit-5
tOD
62
bit-4
Min
bit-3 bit-2 bit-1 bit-0
Typ
±2
BA_LK[2:0]
Max
±4
Design Manual
R/W 33
Units
hex
Def
ns