r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 13

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

6.8
6.9
6.10 Idle Cycle........................................................................................................................... 277
6.11 Write Data Buffer Function ............................................................................................... 297
6.12 Bus Release........................................................................................................................ 298
6.13 Bus Arbitration .................................................................................................................. 302
6.14 Bus Controller Operation in Reset ..................................................................................... 304
6.15 Usage Notes ....................................................................................................................... 305
6.7.10 Byte Access Control ............................................................................................. 228
6.7.11 Burst Operation..................................................................................................... 229
6.7.12 Refresh Control..................................................................................................... 234
6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 240
Synchronous DRAM Interface........................................................................................... 243
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.8.7
6.8.8
6.8.9
6.8.10 Bus Cycle Control in Write Cycle ........................................................................ 254
6.8.11 Byte Access Control ............................................................................................. 255
6.8.12 Burst Operation..................................................................................................... 258
6.8.13 Refresh Control..................................................................................................... 261
6.8.14 Mode Register Setting of Synchronous DRAM.................................................... 268
6.8.15 DMAC and EXDMAC Single Address Transfer Mode and
Burst ROM Interface.......................................................................................................... 274
6.9.1
6.9.2
6.9.3
6.10.1 Operation .............................................................................................................. 277
6.10.2 Pin States in Idle Cycle......................................................................................... 296
6.12.1 Operation .............................................................................................................. 298
6.12.2 Pin States in External Bus Released State ............................................................ 299
6.12.3 Transition Timing ................................................................................................. 300
6.13.1 Operation .............................................................................................................. 302
6.13.2 Bus Transfer Timing............................................................................................. 303
6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 305
6.15.2 External Bus Release Function and Software Standby ......................................... 305
Setting Continuous Synchronous DRAM Space................................................... 243
Address Multiplexing ........................................................................................... 244
Data Bus ............................................................................................................... 245
Pins Used for Synchronous DRAM Interface....................................................... 245
Synchronous DRAM Clock .................................................................................. 247
Basic Timing......................................................................................................... 247
CAS Latency Control............................................................................................ 249
Row Address Output State Control....................................................................... 251
Precharge State Count........................................................................................... 252
Synchronous DRAM Interface ............................................................................. 269
Basic Timing......................................................................................................... 274
Wait Control ......................................................................................................... 276
Write Access......................................................................................................... 276
Rev. 1.00 Sep. 19, 2008 Page xiii of xxviii