r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 717

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Table 11.4 CCLR2 to CCLR0 (Channels 0 and 3)
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
Table 11.5 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
Channel
0, 3
Channel
1, 2, 4, 5
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
buffer register setting has priority, and compare match/input capture does not occur.
modified.
Bit 7
Reserved*
0
Bit 7
CCLR2
0
1
2
Bit 6
CCLR1
0
1
0
1
Bit 6
CCLR1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture*
TCNT cleared by TGRD compare match/input
capture*
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
2
2
Rev. 1.00 Sep. 19, 2008 Page 689 of 1270
Section 11 16-Bit Timer Pulse Unit (TPU)
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REJ09B0466-0100