r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 329

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 6.97 shows the timing for transition to the bus released state with the synchronous DRAM
interface.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Figure 6.97 Bus Release State Transition Timing when Synchronous DRAM Interface
Group.
DQMU, DQML
Precharge-sel
Address bus
SDRAMφ
[1] Low level of BREQ signal is sampled at rise of φ.
[2] PALL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
Data bus
BREQO
BREQ
BACK
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
At least one state from sampling of BREQ signal.
RAS
CAS
CKE
φ
WE
External space read
NOP
T
1
[1]
T
2
[2]
PALL
[3]
address
NOP
Row
[4]
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[5]
Rev. 1.00 Sep. 19, 2008 Page 301 of 1270
[8]
[6]
Section 6 Bus Controller (BSC)
[7]
NOP
[9]
CPU
cycle
REJ09B0466-0100