r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 973

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

16.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls
4. The last byte data is read by reading ICDRR.
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read) and RDRF
is cleared. (Since the read data show the slave address and R/W, it is not used.)
while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge
before reading ICDRR, to be returned to the master device, is reflected to the next transmit
frame.
Slave Receive Operation
Rev. 1.00 Sep. 19, 2008 Page 945 of 1270
Section 16 I
2
C Bus Interface 2 (IIC2)
REJ09B0466-0100