r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 262

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Bus Controller (BSC)
6.7.12
This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing
is used. In addition, self-refreshing can be executed when the chip enters the software standby
state.
Refresh control is enabled when any area is designated as DRAM space in accordance with the
setting of bits RMTS2 to RMTS0 in DRAMCR.
(1)
To select CBR refreshing, set the RFSHE bit to 1 in REFCR.
With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the DRAM used.
When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR
settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is
shown in figure 6.46, compare match timing in figure 6.47, and CBR refresh timing in figure 6.48.
When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is
performed in parallel during the CBR refresh period.
Rev. 1.00 Sep. 19, 2008 Page 234 of 1270
REJ09B0466-0100
RTCOR
H'00
Refresh request
CAS-before-RAS (CBR) Refreshing
Refresh Control
RTCNT
Figure 6.46 RTCNT Operation