r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 192

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Bus Controller (BSC)
6.3.7
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Rev. 1.00 Sep. 19, 2008 Page 164 of 1270
REJ09B0466-0100
Bit
15
14
13
12
11
Bit Name
BRLE
BREQOE
—
IDLC
ICIS1
Bus Control Register (BCR)
0
Initial Value
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Description
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
1: External bus release enabled
BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal bus
master performs an external address space
access, or when a refresh request is generated.
0: BREQO output disabled
1: BREQO output enabled
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Idle Cycle State Number Select
Specifies the number of states in the idle cycle set
by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
Idle Cycle Insert 1
When consecutive external read cycles are
executed in different areas, an idle cycle can be
inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
BREQ, BACK, and BREQO pins can be used
as I/O ports
BREQO pin can be used as I/O port