r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 76
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r4f2426
Manufacturer Part Number
r4f2426
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R4F2426.pdf
(1302 pages)
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Section 2 CPU
•
Rev. 1.00 Sep. 19, 2008 Page 48 of 1270
REJ09B0466-0100
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address.
In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch
address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch
addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of
this range is also used for the exception vector table.
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not
pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception
Handling.
Stack Structure
SP
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
(a) Subroutine Branch
Figure 2.4 Stack Structure in Advanced Mode
Reserved
(24 bits)
PC
(SP *
SP
2
)
(b) Exception Handling
(24 bits)
EXR *
Reserved *
CCR
PC
1
1
*
3
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