r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 306

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Bus Controller (BSC)
(2)
If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle
cycle is inserted at the start of the write cycle.
Figure 6.78 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Rev. 1.00 Sep. 19, 2008 Page 278 of 1270
REJ09B0466-0100
Write after Read
Address bus
CS (area A)
CS (area B)
Data bus
HWR
Figure 6.78 Example of Idle Cycle Operation (Write after Read)
RD
φ
(a) No idle cycle insertion
T
1
(ICIS0 = 0)
Bus cycle A
Long output floating time
T
2
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
φ
T
(b) Idle cycle insertion
1
Bus cycle A
(ICIS0 = 1, initial value)
T
2
T
3
Idle cycle
T
i
Bus cycle B
T
1
T
2