r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 675

no-image

r4f2426

Manufacturer Part Number
r4f2426
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
r4f24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
r4f24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
r4f24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24268NVZFQV
Manufacturer:
REA
Quantity:
150
Part Number:
r4f24268NVZFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24269NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
r4f24269NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
10.15
Port G is a 7-bit I/O port that also has other functions. Port G has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
• Port function control register 0 (PFCR0)
• Port function control register 4 (PFCR4)
• Port G open drain control register (PGODR)
10.15.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be
read; if it is, an undefined value will be read.
Note:
Bit
7
6
5
4
3
2
1
0
Bit Name
PG6DDR
PG5DDR
PG4DDR
PG3DDR
PG2DDR
PG1DDR
PG0DDR
*
Port G
PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7.
0
0
0
0
0
0
0
1/0*
Initial Value
R/W
W
W
W
W
W
W
W
Description
Reserved
Modes 7 (when EXPE = 1), 1, 2, and 4
Pins PG6 to PG4 function as bus control
input/output pins (BREQO, BACK, and BREQ)
when the appropriate bus controller settings are
made. Otherwise, these pins are I/O ports, and
their functions can be switched with PGDDR.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS
output pins when the corresponding PGDDR bit is
set to 1, and as input ports when the bit is cleared
to 0. When the CS output enable bits (CS3E to
CS0E) are cleared to 0, pins PG3 to PG0 are I/O
ports, and their functions can be switched with
PGDDR.
Mode 7 (when EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Rev. 1.00 Sep. 19, 2008 Page 647 of 1270
Section 10 I/O Ports
REJ09B0466-0100

Related parts for r4f2426